1. Field of the Invention
The present invention relates to a semiconductor process and a semiconductor device structure. More particularly, the present invention relates to methods for forming a PN junction, fabricating processes of one-time programmable read-only memory (OTP-ROM) based on the same methods, and structures of OTP-ROM cell and OTP-ROM device fabricated using the same processes.
2. Description of the Related Art
PN junction is a fundamental structure of various semiconductor devices, and is conventionally constituted of polysilicon. However, since polysilicon has many grains of different sizes as well as grain boundaries, the characteristic of polysilicon PN junction is not uniform. In addition, the grain-boundaries of polysilicon induce more leakage paths than single-crystal silicon.
For high-density memory applications, such as the 3D memory, chalcogenide memory, OTP diode or MRAM, steering elements are required to ensure that the current flow is unidirectional. Moreover, uniform characteristics of the memory cells are necessary to increase the sense margin of On-state and Off-state, and decreased leakage current paths are also required to reduce power consumption and heat generation. Therefore, polysilicon PN junctions are not so suitable in high-density memory applications.
For example, U.S. Pat. No. 6,420,215 discloses a structure of a three-dimensional (3D) OTP-ROM, which is formed by alternately stacking layers of parallel N-type polysilicon lines and layers of parallel P-type polysilicon lines. In any two adjacent layers, the orientation of the parallel N-type polysilicon lines is different from that of the parallel P-type polysilicon lines, and a pair of N-type polysilicon line and P-type polysilicon line is separated by an antifuse layer. The overlapping portions of a pair of N-type polysilicon line and P-type polysilicon line and the antifuse layer between them together constitute a memory cell. During the programming operation of the 3D OTP-ROM, a forward bias is applied between a pair of selected N-type polysilicon line and P-type polysilicon line to break down the antifuse layer between them and thereby form a PN junction. However, since the polysilicon PN junctions lack uniform characteristic and have grain boundaries, as mentioned above, the characteristics of the memory cells are not uniform, and a leakage current is easily induced under reverse bias.
A possible method for solving the aforementioned problems of polysilicon PN junction is to control the sizes of polysilicon grains and the locations of grain boundaries. For example, Yonehara et al. disclosed a method for controlling grain boundaries in Materials Research Society, Symp. Proc. Vol. 106, p. 21-26 (1988), which utilizes a selective nucleation process over an amorphous substrate. Specifically, a high-nucleation-density layer (e.g., a Si3N4 layer) formed on a low-nucleation-density layer (e.g., a SiO2 layer) is patterned into small blocks to serve as nucleation sites. Alternatively, a low-nucleation-density layer formed on a high-nucleation-density layer is patterned to expose small regions of the high-nucleation-density layer to serve as nucleation sites. A gas-phase epitaxial process is then performed to form silicon grains having the same distribution of the nucleation sites. However, since an additional mask is required to pattern the high-nucleation-density layer or the low-nucleation-density layer in the method, the fabricating process is more tedious.
Another possible method for solving the aforementioned problems of conventional PN junction is to use single-crystal silicon material for forming the PN junction. For example, Subramanian et al. disclosed a method for forming a source/drain and a channel in single-crystal silicon in IEEE EDL, Vol. 20, No. 7, p. 341-343 (1999). In the method, a sacrificial oxide layer is formed on an amorphous silicon layer, a small aperture is formed in the sacrificial oxide layer, and then a germanium (Ge) seed layer is selectively formed on the amorphous silicon layer exposed by the small aperture. An annealing process is performed to recrystallize the amorphous silicon layer starting from the portion adjacent to the Ge seed layer, so that the amorphous silicon layer is gradually converted into a single-crystal silicon layer. The Ge seed layer and the sacrificial oxide layer are then removed, and a source/drain region and a channel region are defined in the single-crystal silicon layer. However, since an additional mask is also required to pattern the sacrificial oxide layer, the fabricating process is more tedious.